The present invention relates to a storage device and is suitably applicable to a semiconductor storage device having a plurality of memories (or memory chips).
Various types of storage devices having a plurality of memories for storing data have been in wide use. Some of the recently popularized semiconductor storage devices have each a plurality of nonvolatile memories (namely, flash memories) as memory functionality (refer to Japanese Patent Laid-open No. Sho 64-78354).
These recent semiconductor storage devices are each designed for connection with an information processing apparatus such as personal computers to function as external storage devices for storing data from the connected information processing apparatus.
Now, with reference to FIG. 7, there is shown an exemplary configuration of such a semiconductor storage device as mentioned above. This semiconductor storage device has a first nonvolatile memory and a second nonvolatile memory to which data is written and a controller block for sending data to be written to each of the first nonvolatile memory and the second nonvolatile memory. In this example, each of the first and second nonvolatile memories has 8-bit data input/output terminals and the controller block also has 8-bit data input/output terminals.
The controller block is connected to the first nonvolatile memory via a data communication line group made up of eight data communication lines (namely a data bus with 8-bit bus width) for example and connected to the second nonvolatile memory via a data communication line group separated from the above-mentioned data communication line group.
As shown in FIG. 8 for example, after the controller block has transmitted data to be written to the first nonvolatile memory via the data communication line group (timing T10), the first nonvolatile memory executes internal processing for writing the received data to an internal storage area thereof. Upon successful completion of this internal processing, the first nonvolatile memory transmits a signal for telling the completion (hereafter referred to as “completion notice signal”) to the controller block via the data communication line group (timing T20).
Consequently, in this semiconductor memory device, the data communication line group is kept in an occupied state by the data communication between the controller block and the first nonvolatile memory until the controller block receives the completion notice signal from the first nonvolatile notice signal (timing T20) even after the controller block has transmitted the data to the first nonvolatile memory (timing T10).
This presents a problem in processing efficiency owing to the fact that, although this controller block is ready for starting data transmission processing to transmit data to the second nonvolatile memory at timing T10, the controller block cannot actually start the data transmission processing until timing T20 at which the occupied data communication line group is available.